1. Field of the Invention
The present invention relates to a SRAM built-in self test (SRAM BIST) circuit, and more particularly, to an address generator and a method of generating an address and an SRAM BIST using the same.
2. Description of the Related Art
In general, as semiconductor devices become more complicated and highly integrated, research is underway on various methods for effectively testing the semiconductor devices. In particular, memory built-in self test (BIST) methods have been developed for effectively testing a memory in a semiconductor device using a BIST circuit implemented in connection with memory test processes.
A SRAM BIST circuit typically includes a BIST controller for controlling BIST operation, a data generator for generating data to be written to the SRAM, an address generator for generating an address for the SRAM, a comparator for comparing data read from the SRAM, and a counter for counting steps of the test process. A typical address generator performs both up counting and down counting according to the test procedure. However, when the address generator is produced using such an up/down counter, there are difficulties in obtaining an optimized chip area. For example, when the number of addresses in the SRAM to be tested is 2.sup.n, where n is the number of bits in a SRAM memory address, the address generator can be readily realized using the up/down counter; however, the chip area of the address generator is relatively large. When the number of addresses in the SRAM to be tested is not 2.sup.n and the address generator is realized using the up/down counter, other additional circuitry which interfaces with the up/down counter is required, and the chip area of the address generator becomes even larger.